This application relies for priority upon Korean Patent Application No. 99-17600, filed on May 17, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method for fabricating a semiconductor device and a resulting semiconductor device fabricated by this method. More particularly, the present invention relates to a method for fabricating a flash memory device and a resulting flash memory device fabricated by such a method.
In contrast to a random access memory (RAM) device, a flash memory device, which is a type of a read only memory (ROM), does not lose information stored in its memory cells, even if its power supply is interrupted. Because of this characteristic, flash memory devices are being widely adopted in memory cards for computers and the like.
A unit cell of a flash memory device has the same structure as that of a memory cell of an erasable programmable ROM (EPROM) device or an electrically erasable and programmable ROM (EEPROM) device. In other words, a flash memory cell includes a tunnel oxide film, a floating gate, an inter-gate dielectric film, and a control gate electrode serving as a word line, which are sequentially stacked on a channel region.
FIG. 1 is a layout showing part of a cell array of a conventional NAND-type flash memory device. Referring to FIG. 1, two active regions ACT are disposed in parallel. One string selection line SSL, a plurality of word lines WL1, WL2, . . . , and WLn, and one ground selection line GSL are also disposed in parallel, but oriented to cross the two active regions ACT in a perpendicular direction. A contact CT exposing each active region ACT is placed on each active region ACT adjacent to the string selection line SSL.
Bit lines BL1 and BL2, which are electrically connected to respective active regions ACT via each contact CT, run over each active region ACT. The active regions ACT adjacent to the ground selection line GSL are extended in a direction parallel to the ground selection line GSL so as to serve as a common source line CSL.
A floating gate isolation pattern FGI is disposed in a region between the two active regions ACT, i.e., to serve as a device isolation region. The floating gate isolation pattern FGI is disposed such that it crosses only the plurality word lines WL1, WL2, . . . , and WLn placed between the string selection line SSL and the ground selection line GSL.
A single memory cell, i.e., a single cell transistor, is formed at the intersection of each word line WL1, WL2, . . . , and WLn and each active region ACT. A gate of each cell transistor has a structure in which a tunnel oxide film, a floating gate FG (the hatched portion in FIG. 1), an inter-gate dielectric film, and a control gate electrode corresponding to a word line are sequentially stacked on the active region ACT.
FIGS. 2A, 3A and 4A are sectional views taken along the line A-Axe2x80x2 of FIG. 1, to explain a method of fabricating the conventional flash memory device. FIGS. 2B, 3B and 4B are sectional views taken along the line B-Bxe2x80x2 of FIG. 1, also to explain a method for fabricating the conventional flash memory device.
Referring to FIGS. 2A and 2B, a device isolation film 3 is formed in a predetermined region of a semiconductor substrate 1, using a photo mask on which the active region ACT of FIG. 1 is engraved. A thin tunnel oxide film 5 having a thickness of 100 xc3x85 or less is formed on the surface of the active region between the device isolation films 3. A first conductive layer, e.g., a doped polysilicon film, is formed on the entire surface of the semiconductor substrate on which the tunnel oxide film 5 has been formed. A first conductive layer pattern 7 for exposing a predetermined region of the device isolation film 3 between the adjacent active regions is formed by patterning the first conductive layer using a photo mask on which the floating gate isolation pattern FGI is engraved.
Referring to FIGS. 3A and 3B, an inter-gate dielectric film 9 and a second conductive layer are sequentially formed on the entire surface of the semiconductor substrate on which the first conductive pattern 7 has been formed. The second conductive layer, the inter-gate dielectric film 9 and the first conductive layer pattern 7 are consecutively patterned using a photo mask on which the plurality of word lines WL1, WL2, . . . , and WLn of FIG. 1 are engraved. Accordingly, the plurality of word lines WL1, WL2, . . . , and WLn, which are parallel to one another, are formed and, simultaneously, the floating gate FG of FIG. 1 is formed on the active region crossing each word line WL1, WL2, . . . , and WLn.
At this time, the inter-gate dielectric film 9 remaining at the sidewalls of the first conductive layer pattern 7 between the plurality of word lines WL1, WL2, . . . , and WLn should be completely removed. If a part of the inner-gate dielectric film 9 remains on the sidewalls of the first conductive layer pattern 7 between the plurality of word lines WL1, WL2, . . . , and WLn, the first conductive layer pattern 7 between the plurality of word lines WL1, WL2, . . . , and WLn is also not completely removed, thereby forming a stringer of the first conductive material. The stringer can electrically connect adjacent floating gates FG to each other. This can cause a problem in which an unselected second cell is also programmed when a selected first cell is being programmed.
As a result of this, the inter-gate dielectric film 9, which is exposed after the second conductive layer is etched, should be over etched. This results in a recess of the device isolation film 3 exposed between the plurality word lines WL1, WL2, . . . , and WLn, as shown in FIG. 3B, thereby reducing the thickness of the device isolation film 3. Of course, the recess phenomenon in the device isolation film 3 becomes more serious as the first conductive layer pattern 7 becomes thicker, requiring greater etching to remove.
Referring to FIGS. 4A and 4B, impurities of a different conductivity type to that of the semiconductor substrate 1 are implanted into the active region exposed between the plurality of word lines WL1, WL2, . . . , and WLn, thereby forming source and drain regions SD1 and SD2, respectively, for each cell transistor. At this time, as shown in FIGS. 4A and 4B, the impurities may also be implanted into the semiconductor substrate 1 under the recessed device isolation film 3, thereby forming a field inversion layer FI. Accordingly, an electrical isolation characteristic between adjacent source and drain regions SD1 and SD2 is reduced so that a leakage current Ib may flow when different voltages are applied to the source and drain regions SD1 and SD2. Consequently, when selectively programming one cell of the flash memory device fabricated according to the conventional technology described above, it is possible that an unselected memory cell may also be programmed.
With reference to FIGS. 1, 4A, and 4B, general conditions required for programming a selected memory cell S will now be described. Primarily, the voltage of 0V is applied to a selected bit line connected to a string including the selected memory cell S, e.g., the first bit line BL1, and a program inhibition voltage VPpi that is close to a power supply voltage Vcc is applied to the unselected bit lines, e.g., the second bit line BL2. A program voltage Vp of about 15V is applied to a selected word line that serves as a control gate electrode of the selected memory cell S, e.g., the second word line WL2. A pass voltage Vpass of about 8V is then applied to unselected word lines WL1, . . . , and WLn other than the selected word line (WL2 in this example) and the string selection line SSL. The voltage of 0V is applied to the ground selection line GSL, the common source line CSL, and the semiconductor substrate 1.
As describe above, once a predetermined voltage is applied to each control line for the purpose of programming the selected memory cell, the voltage of 0V is induced to the source and drain region SD1 and a channel region CH1 of the selected memory cell S and the program inhibition voltage Vpi is induced to the source and drain region SD2 and a channel region CH2 of a unselected memory cell N, which is adjacent to the selected memory cell S and which shares the second word line WL2 with the selected memory cell S. At this time, if the width and thickness of the device isolation film 3 do not both exceed respective predetermined values, a parasitic field transistor between the unselected memory cell N and the selected memory cell S may be turned on by the high program voltage Vp applied to the second word line WL2.
As a result of this parasitic field transistor, a leakage current Ia may flow from the channel region CH2 of the unselected memory cell N to the channel region CH1 of the selected memory cell S. Furthermore, in a case where the field inversion layer FI is formed under the device isolation film 3 between the source and drain region SD2 of the unselected memory cell N and the source and drain region SD1 of the selected memory cell S, another leakage current Ibmay flow between the source and drain regions SD2 and SD1. As a result, a ground voltage may be induced in the channel region CH2 of the unselected memory cell N, thereby causing the unselected memory cell N to be programmed.
According to the conventional technology as described above, a device isolation characteristic between a selected memory cell and an unselected memory cell is reduced so that even the unselected memory cell is programmed. Furthermore, the conventional technology has a limitation in that it is harder to reduce the width and thickness of a device isolation film for the purpose of increasing the integration of a flash memory device.
It is an object of the present invention to provide a method for fabricating a flash memory device for preventing a device isolation film between adjacent memory cells from being recessed even if a floating gate of the memory cell is thicker than the device isolation film.
It is another object of the present invention to provide a flash memory device having an improved coupling ratio for each memory cell and an improved device isolation characteristic between adjacent memory cells.
To achieve the first object of the present invention, a method is provided for fabricating a flash memory device. This method comprises forming a device isolation film over a predetermined region of a semiconductor substrate to define a plurality of active regions, forming a tunnel insulating film over the active regions, forming a plurality of floating gate patterns in parallel, such that they cross the device isolation film and the active regions, each of the plurality of floating gate patterns comprising a conductive layer pattern and a capping layer pattern that are sequentially stacked, forming a plurality of impurity regions of a different conductivity type from that of the semiconductor substrate in a portion of the active region between the plurality of floating gate patterns, forming an insulating film pattern to fill up regions between the plurality of floating gate patterns, forming a plurality of floating gates and isolated capping layers that are sequentially stacked over respective active regions by selectively etching a predetermined region of each floating gate pattern to expose a portion of the device isolation film beneath each floating gate pattern, exposing each floating gate by removing the isolated capping layers, forming an inter-gate dielectric film over the exposed floating gate and the exposed device isolation film and forming a plurality of word lines over the inter-gate dielectric film, such that each word line crosses the device isolation film and the active regions. The impurity region is preferably formed by implanting phosphorus (P) or arsenic (As) ions at a dose of between 1xc3x971013 ion atoms/cm2 to 1xc3x971014 ion atoms/cm2.
The method may further comprise forming spacers at sidewalls of the floating gate patterns. The method may then further comprise forming a high concentration impurity region by implanting arsenic (As) ions at a dose of between 1xc3x971015 ion atoms/cm2 to 5xc3x971015 ion atoms/cm2 in the impurity region, using the spacers and the floating gate pattern as an ion-implantation mask, after forming the spacers.
The forming of the insulating film pattern may comprise forming an insulating film over the impurity regions, and blanket-etching the insulating film until the capping layer pattern in the floating gate pattern is exposed.
The method may further comprise forming a channel stop impurity region by implanting impurities of the same conductivity type as the semiconductor substrate in the semiconductor substrate under the exposed device isolation film, after forming the floating gates and isolated capping layers.
The forming of the plurality of word lines may comprise forming a conductive layer over portions of the semiconductor substrate from which the isolated capping layers have been removed, and forming a plurality of conductive layer patterns insulated by the inter-gate dielectric film over the floating gate and the device isolation film adjacent to the floating gate by patterning the conductive layer and the inter-gate dielectric film to expose the insulating film pattern. The plurality of conductive layer patterns are preferably formed in parallel in a direction in which the plurality of conductive layer patterns cross the device isolation film.
The conductive layer preferably comprises tungsten polycide.
The forming of the plurality of word lines may comprise forming a polysilicon film over portions of the semiconductor substrate from which the isolated capping layers have been removed, forming a plurality of polysilicon patterns insulated by the inter-gate dielectric film over the floating gate and the device isolation film adjacent to the floating gate by blanket-etching the polysilicon film until the insulating film pattern is exposed, wherein the plurality of polysilicon patterns are formed in parallel in a direction in which the plurality of polysilicon patterns cross the device isolation film, and selectively forming a refractory metal silicide film over the plurality of polysilicon patterns.
The method may further comprise forming an interlayer insulating film over the semiconductor substrate and the plurality of word lines, forming a bit line contact hole exposing a predetermined region of the active region by patterning the interlayer insulating film, and forming a bit line over the interlayer insulating film, the bit line being electrically connected to the exposed active region through the bit line contact hole.
To achieve the second object of the present invention, a flash memory device is provided, comprising a pair of device isolation films formed in a predetermined region of a semiconductor substrate to define an active region, a tunnel insulating film formed over the active region, a floating gate covering a predetermined area of the tunnel insulating film and extending over the edges of the pair of device isolation films adjacent to the predetermined area of the tunnel insulating film, the floating gate being thicker than the device isolation film, an inter-gate dielectric film formed over the floating gate, and a word line formed over the inter-gate dielectric film, the word line serving as a control gate electrode.
The center of the device isolation films are no thinner than the edges of the pair of device isolation films overlapped with the floating gate.
According to the present invention described above, a device isolation film between a plurality of floating gates maintains its initial thickness even if the floating gate is thicker than the device isolation film. Therefore, not only is an area in which a word line is overlapped with the floating gate increased but also the device isolation characteristic between adjacent cells is prevented from being reduced.